Mark focuses on the preparation and prosecution of patent applications and technical litigation support, primarily in the electrical engineering and computer science fields. His practice includes prosecuting and defending patent post-grant review proceedings, assisting with domestic and foreign patent litigation, and counseling clients regarding patent infringement and validity.
Mark has 11 years of experience developing electronic design automation (EDA) software tools and related methodologies for high performance integrated circuit designs. His technical expertise spans a number of fields in the electrical engineering and computer science disciplines, including VLSI design, computer architecture, analog and digital circuits, semiconductors, signal processing, integrated circuit inspection and test, power and control systems, electrical power grids and alternative energy, cloud computing, computer graphics, and software engineering. Mark also has experience preparing and prosecuting patent applications in the mechanical, nanotechnology, and business method arts.
Mark first joined Klarquist as a summer associate in 2007, returned as an associate in 2008, and became partner in 2016.
- J.D., cum laude, Lewis & Clark Law School, 2008
- B.S., Electrical and Computer Engineering, Carnegie Mellon University, 1995
- Oregon, 2009
- U.S. Patent and Trademark Office, 2008 (Reg. No. 63,126)
- U.S. Court of Appeals for the Federal Circuit
- U.S. District Court for the District of Oregon
- U.S. District Court for the Eastern District of Texas
Electrical & Semiconductors
Software & Internet Technology
1995 – 2007
While at Intel, Mark developed design and verification EDA tools for leading-edge deep submicron designs, including the Intel Pentium® II, Pentium® 4, and Core™ i7 microprocessors. In addition, he managed a team of design automation engineers, and served as an invention disclosure reviewer for the Intel Legal Software IP committee.
Carnegie Mellon Research Institute
1993 – 1994
Designed, built, and tested wired and wireless industrial control and solid state gas sensor prototypes.
- Chair, Oregon State Bar IP Section, 2021; Executive Committee 2017-present
- Member, American Intellectual Property Law Association
- Member, Oregon Patent Law Association
- Member, Association of Computing Machinery
Honors & Awards
- 2017 – 2020 Oregon Super Lawyers® Rising Star
- Three Intel Division Awards (outstanding execution in layout verification and tapeout for a 90 nm microprocessor (2003), analysis and implementation of layout fixes for yield increase for a 0.18 μm processor (2001), and development of an incremental parameterized standard cell layout methodology (2007))
Presentations & Publications
- Invention Disclosure Meetings, CLE presentation, Klarquist Sparkman, LLP, June 2019.
- Patent Drafting for Effective US/EP Prosecution, Fortune 500 client presentation, May 2019.
- Guest Lecturer on IP for engineers, Engineering for Professional Practice, Portland State University, 2016-present.
- Patent Eligibility Practice Considerations for Software, CLE Presentation, Battelle Memorial Institute, June 2014.
- Drafting Invalidity and Non-infringement Opinions, CLE presentation, Klarquist Sparkman, LLP, January 2013.
- Post-Grant Proceedings after the AIA, CLE presentation, Tonkon Torp, LLP, November 2012.
- Why Private Remedies for Environmental Torts Under the Alien Tort Statute Should Not Be Constrained by the Judicially Created Doctrines of Jus Cogens and Exhaustion, 39 Envtl. L. 451 (2009).
- Co-authored three papers for the Intel Design & Test Technology conference, including: Novel Features & Methodology to Increase Physical Design for Debug Coverage by 10X, Rapid Interconnect Design Through the Use of Virtual Repeaters, and Willamette Stretchable Cell Layout Methodology.